Systems and methods for load detection and correction in a digital amplifier

ABSTRACT

Systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the response of the amplifier. One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.

RELATED APPLICATIONS

This application claims priority to U.S. Patent application Ser. No.10/805,741, entitled “Systems And Methods For Automatically AdjustingChannel Timing,” by Taylor, et al., filed Mar. 22, 2004, which claimspriority to: U.S. Provisional Patent Application No. 60/456,421,entitled “Output Device Switch Timing Correction,” by Taylor, et al.,filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,414,entitled “Adaptive Anti-Clipping Protection,” by Taylor, et al., filedMar. 21, 2003; U.S. Provisional Patent Application No. 60/456,430,entitled “Frequency Response Correction,” by Taylor, et al., filed Mar.21, 2003; U.S. Provisional Patent Application No. 60/456,429, entitled“High-Efficiency, High-Performance Sample Rate Converter,” by Anderson,et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No.60/456,422, entitled “Output Filter, Phase/Timing Correction,” byTaylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent ApplicationNo. 60/456,428, entitled “Output Filter Speaker/Load Compensation,” byTaylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent ApplicationNo. 60/456,420, entitled “Output Stage Channel Timing Calibration,” byTaylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent ApplicationNo. 60/456,427, entitled “Intelligent Over-Current, Over-LoadProtection,” by Hand, et al., filed Mar. 21, 2003; each of which isfully incorporated by reference as if set forth herein in its entirety.

BACKGROUND

1. Field of the Invention

The invention relates generally to audio amplification systems, and moreparticularly to systems and methods for detecting the impedance of anoutput load coupled to a digital amplifier and compensating for changesin the frequency response of the amplifier.

2. Related Art

Pulse Width Modulation (POMPWM) or Class D signal amplificationtechnology has existed for a number of years. POM PWM technology hasbecome more popular with the proliferation of Switched Mode PowerSupplies (SUMPSSMPS). Since this technology emerged, there has been anincreased interest in applying POM PWM techniques in signalamplification applications as a result of the significant efficiencyimprovement that can be realized through the use of Class D power outputtopology instead of the legacy (linear Class TAB) power output topology.

Early attempts to develop signal amplification applications utilized thesame approach to amplification that was being used in the early SUMPSSMPS. More particularly, these attempts utilized analog modulationschemes that resulted in low performance applications. Theseapplications were complex and costly to implement. Consequently, thesesolutions were not widely accepted. Prior art analog implementations ofClass D technology have therefore been unable to displace legacy ClassTAB amplifiers in mainstream amplifier applications.

Recently, digital POM PWM modulation schemes have surfaced. Theseschemes use Sigma-Delta modulation techniques to generate the POM PWMsignals used in the newer digital Class D implementations. These digitalPOM PWM schemes, however, did little to offset the major barriers tointegration of POM PWM modulators into the total amplifier solution.Class D technology has therefore continued to be unable to displacelegacy Class TAB amplifiers in mainstream applications.

One of the problems with prior art systems and methods is that thequality and performance of the discrete output power switches and theirassociated drivers is unknown and varies as the performance and demandof the application change.

Another problem with prior art systems and methods is that theperformance and quality characteristics of the remainder of the signalprocessing system vary with the applications in which they are used.Because the exact implementation in each system and the end-userapplications are not deterministic, each system requires a pointsolution. These point solutions are not flexible, scaleable ortransportable across applications.

Yet another problem with prior art systems and methods is that theirfrequency responses vary with changes in the respective load impedances.In a conventional open loop system, an output reconstruction filterproduces a low-pass filter response that is dependent upon the outputload. As the load of a particular system is increased, the highfrequency response of the system decreases in a predictable manner.

Because of these problems with the prior art, it would be desirable toprovide systems and methods to detect changes in output loads and tocompensate for these changes to maintain an optimal frequency responseand optimal performance.

SUMMARY OF THE INVENTION

One or more of the problems outlined above may be solved by the variousembodiments of the invention. Broadly speaking, the invention comprisessystems and methods for detecting the impedance of an output loadcoupled to a digital amplifier and compensating for changes in thefrequency response of the amplifier.

One embodiment of the invention is implemented in a Class D pulse widthmodulated (POMPWM) amplifier. In this embodiment, a digital POM PWM testsignal is generated. This test signal is processed by the amplifier toproduce a corresponding analog audio output signal that is used to drivea speaker. A sense resistor placed in series with the speaker is used togenerate a test voltage that is compared to a reference voltage. Whenthe test voltage reaches the reference voltage, the current through thesense resistor (hence the speaker) is at a known level, so the value ofthe digital test signal is noted. The impedance of the speaker is thendetermined from the test signal value and the speaker current.

After the speaker impedance has been determined, the signal processingthat is performed by the amplifier can be automatically adjusted tooptimize the processing for the computed speaker impedance. Theamplifier can thereby compensate for increased high-frequency responsethat would otherwise occur with higher-impedance loads and decreasedhigh-frequency response that would occur with lower-impedance loads. Inone embodiment, the impedance of the speaker is determined using testsignals having multiple, different frequencies. This results in animpedance profile for the speaker, which may be used as the basis formodifying the signal processing performed by the amplifier. In oneembodiment, the impedance profile can be compared to a library ofprofiles corresponding to specific speakers. If the impedance profilematches one of the library profiles, the speaker can be identified, andthe audio signal processing performed by the amplifier can be optimizedaccording to known parameters that are associated with the identifiedspeaker.

One alternative embodiment comprises a method implemented in a digitalamplifier. The method includes generating a digital test signal,converting the digital test signal to an analog signal and driving aload with the analog signal. A threshold level of current through theload is detected and the value of the digital test signal that generatedthe threshold level of current through the load is identified. Based onthis information, an impedance is calculated for the load at thefrequency of the test signal. The method can be repeated for multipletest signal frequencies to create an impedance profile. The impedanceinformation can be used to automatically adjust the frequency responseand/or other operating parameters of the amplifier. In one embodiment,the calculated impedance profile is compared to a library of profilesfor known speakers, and if it matches one of the profiles, operatingparameters for the corresponding speaker are implemented.

Another alternative embodiment comprises a digital amplifier thatincludes a digital test signal generator, a digital engine configured toconvert the test signal to an analog signal, and an output stage. Theoutput stage is configured to receive the analog signal and to drive aload and a sense resistor that is in series with the load. A comparatorreceives the voltage across the sense and a reference voltage which isequal to the resistance of the sense resistor times a threshold level ofcurrent. The comparator generates a binary signal indicating whether thevoltage across the sense resistor exceeds the reference voltage. Thisbinary signal is provided to a processor that identifies the value ofthe digital test signal corresponding to transitions in the binarysignal. The processor then calculates an impedance of the load based onthe threshold level of current and the value of the digital test signalcorresponding to the transition in the binary signal. The amplifier maybe configured to vary the frequency of the test signal and to determinethe impedance of the load for various frequencies. Based on theimpedance information, the processor automatically adjusts theprocessing input signals to optimize its performance for the detectedload.

Numerous other embodiments are also possible.

The various embodiments of the present invention may provide a number ofadvantages over the prior art. For example, the embodiments of thepresent invention may be much less complex and easier to implement andmaintain than in comparable prior art systems. Prior art systems thatattempt to perform load detection typically measure output current andvoltage with RMS-to-DC converters, then perform an A/D conversion on thefull measured values, and then calculate the result of the voltagedivided by the current. The present embodiments instead perform a simplecomparison of analog values and produce a binary over-threshold signal.Another advantage that may be provided by embodiments of the inventionis the automatic adjustment of the system processing in response to thedetected load. Prior art systems typically require manual adjustment ofoperating parameters by a user. Present embodiments may adjust thefrequency response of the amplifier in response to a one or more outputload values, or may adjust other operating parameters that correspond toa particular speaker that is identified by comparing a calculatedimpedance profile to a library of profiles. Still other advantages mayalso be provided by the various embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention may become apparent uponreading the following detailed description and upon reference to theaccompanying drawings.

FIG. 1 is a functional block diagram illustrating a POM PWMamplification system in accordance with one embodiment of the invention.

FIG. 2 is a more detailed diagram illustrating a digital POM PWMamplifier in accordance with one embodiment.

FIG. 3 is a flow diagram illustrating a method for determining theimpedance of a load on the output of a digital amplifier in accordancewith one embodiment.

FIG. 4 is a flow diagram illustrating a method for generating animpedance profile for a load on the output of a digital amplifier inaccordance with one embodiment.

FIG. 5 is a functional block diagram illustrating a digital POM PWMamplifier in accordance with one alternative embodiment.

FIG. 6 is a diagram illustrating the linear increase/decrease of currentthrough the sense resistor as a function of time in accordance with oneembodiment.

While the invention is subject to various modifications and alternativeforms, specific embodiments thereof are shown by way of example in thedrawings and the accompanying detailed description. It should beunderstood, however, that the drawings and detailed description are notintended to limit the invention to the particular embodiment which isdescribed. This disclosure is instead intended to cover allmodifications, equivalents and alternatives falling within the scope ofthe present invention as defined by the appended claims.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

One or more embodiments of the invention are described below. It shouldbe noted that these and any other embodiments described below areexemplary and are intended to be illustrative of the invention ratherthan limiting.

As described herein, various embodiments of the invention comprisesystems and methods for detecting the impedance of an output loadcoupled to a digital amplifier and compensating for changes in thefrequency response of the amplifier. One embodiment is implemented in aClass D pulse width modulated (POMPWM) amplifier. A mechanism isprovided for determining the impedance of a speaker that is coupled tothe output of the amplifier. The processing of the digital audio signalis then adjusted if necessary to optimize the frequency response of theamplifier for the specific impedance of the speaker.

In this embodiment, a digital test signal (e.g., a sine wave) isgenerated. This test signal is processed by the amplifier to produce acorresponding analog audio output signal that is used to drive thespeaker. The current through the speaker is determined and used inconjunction with the test signal that produced the current to determinethe impedance of the speaker. More specifically, the current through thespeaker is used to generate a test voltage that is compared to areference voltage. When the test voltage reaches the reference voltage,the value of the digital test signal is noted. The impedance of thespeaker is then determined from this information.

After the impedance has been determined, the signal processing that isperformed by the amplifier can be automatically adjusted to optimize theprocessing for the computed speaker impedance. The amplifier can therebycompensate for increased high-frequency response that would otherwiseoccur with higher-impedance loads and decreased high-frequency responsethat would occur with lower-impedance loads.

In one embodiment, the process of generating a test signal anddetermining the digital signal level at which the test voltage reachesthe reference voltage is repeated for a variety of different testsignals to produce an impedance profile for the speaker. This impedanceprofile may be used as the basis for modifying the signal processingperformed by the amplifier. In one embodiment, the impedance profile canbe compared to a library of profiles corresponding to specific speakers.If the impedance profile matches one of the library profiles, thespeaker can be identified, and the audio signal processing performed bythe amplifier can be optimized according to known parameters that areassociated with the identified speaker.

Referring to FIG. 1, a functional block diagram illustrating a POM (PWM)amplification system in accordance with one embodiment of the inventionis shown. As depicted in the figure, POM (PWM) amplification system 100comprises an internal processor 110, a delta-sigma converter 120, a POMPCM-to-POMPWM modulator 130, a Driver 150, an output stage 160, aspeaker 170 and a feedback subsystem 180. Delta-sigma converter 120 andPOM PCM-to-POMPWM modulator 130 form a Class D modulator 140.

In normal operation, a digital audio signal is provided to processor 110of the amplifier. Processor 110 performs audio processing on thereceived digital signal. Processor 110 may perform various types ofprocessing on the signal, including pre-correction of the signal thatwill compensate for a non-optimal frequency response in the remainder ofthe amplifier. The processed digital audio signal is then converted to a1-bit, pulse width modulated digital data stream by Class D modulator140. This 1-bit data stream is characterized by two control signals thatare output to driver 150, which then uses the signals to drive the upperand lower switches of output stage 160. The signal produced by outputstage 160 can then be used to drive a speaker 170.

The structure of the amplifier in FIG. 1, with the exception of feedbacksubsystem 180, is very similar to a more conventional digital POM (PWM)amplifier. As in conventional amplifiers, the processing of digitalaudio signals by the amplifier to produce analog output signals variessomewhat with frequency. Ideally, the frequency response of theamplifier would be flat across all audio frequencies. In practice,however, it may be difficult to achieve this ideal. Various types ofprocessing (e.g., filtering) of the digital data are employed in anattempt to optimize (flatten) the frequency response of the amplifier.Typically, however, the processing performed by the amplifier isoptimized for a point solution that incorporates a specific speakerimpedance. If a speaker having a higher impedance is used, the frequencyresponse tends to increase at higher frequencies. If a speaker having alower impedance is used, the frequency response tends to droop at higherfrequencies. The present embodiment therefore incorporates a mechanismto determine the impedance of the speaker and to adjust the frequencyresponse if necessary to correspond to this impedance.

The Speaker impedance detection and compensation mechanism includesfeedback subsystem 180. Feedback subsystem 180 is coupled to outputstage 160 and is configured to detect a threshold level of currentthrough speaker 170. When this threshold level of current is detected, afeedback signal that is provided to processor 110 is asserted. Thisfeedback signal may also be referred to herein as an “over-threshold”signal, since the signal is asserted when the current through thespeaker is over a threshold level. The assertion of the feedback signalis used by processor 110 to identify the value of a digital test signalthat caused the speaker current to reach the threshold level. This valueis then used by processor 110 to determine the impedance of speaker 170at the frequency of the test signal.

It should be noted that the structure illustrated in FIG. 1 is merelyexemplary. Other embodiments may incorporate more or fewer components,or may have alternative configurations.

Referring to FIG. 2, a more detailed diagram illustrating a digital POM(PWM) amplifier in accordance with one embodiment is shown. As depictedin this figure, the processor of the amplifier is implemented using adigital signal processor (DIPDSP) 210. DIP DSP 210 includes a testsignal generator 211. Test signal generator 211 is configured togenerate pulse code modulated (POMPCM) test signals that are provided toPOM PWM engine 240. POM PWM engine 240 converts the stream of POM PCMaudio data that is received from DIP DSP 210 into POM PWM audio data.The POM PWM data is provided to driver/level shifter 250, which producesa pair of signals to drive high-side and low-side switching transistors261-264 in the output stage. Transistors 261-264 are switched on and offto allow current to flow through speaker 270, as well as through CLfilters (consisting of inductors 265 and 267, and capacitors 266 and268) on either side of the speaker. The feedback mechanism in thisembodiment consists of a resistor 281 positioned in series with speaker270, and a differential amplifier 282. Differential amplifier 282receives the voltage across resistor 281 and a reference voltage asinputs, and provides an output signal indicating which of the voltagesis higher to DIP DSP 210.

The amplifier of FIG. 2 operates in essentially the following manner.Signal generator 211 generates a test signal that consists of a sinewave having a particular frequency and a particular amplitude. As notedabove, the test signal consists of digital POM PCM data. The POM PCMtest signal is converted by POM PWM engine 240 into a POM PWM signal,which is used by driver/level shifter 250 to generate high-side andlow-side switching signals. These switching signals are essentiallyinverses of each other, aside from minor timing differences that neednot be discussed here. When the high-side signal is asserted and thelow-side signal is not, transistors 261 and 264 are switched on, andtransistors 262 and 263 are switched off. Current therefore flows fromthe voltage source through transistor 261, inductor 265, speaker 270,inductor 267, transistor 264 and resistor 281. When the low-side signalis asserted and the high-side signal is not, transistors 262 and 263 areswitched on, and transistors 261 and 264 are switched off. Current thenflows from the voltage source through transistor 263, inductor 267,speaker 270, inductor 265, transistor 262 and resistor 281.

It is apparent that, whether the high-side or low-side signal isasserted (i.e., whether current is flowing in one direction or theother,) the current through speaker 270 also flows through resistor 281.The size of resistor 281 is chosen to be small (e.g., 50 mΩ) in order tominimize the effect of the resistor in the circuit. Since the voltageacross resistor 281 is equal to the current through the resistor timesthe resistance of the resistor (i.e., V=AIR,) the voltage across theresistor is proportional to the current through the resistor (andthrough speaker 270.) Thus, when the voltage across resistor 281 reachesa threshold level, the current through the resistor and speaker 270 isat a corresponding threshold current level. The threshold voltage levelacross resistor 281 is determined by the reference voltage that is inputto differential amplifier 282. When the voltage across resistor 281 isless than the reference voltage, the signal at the output ofdifferential amplifier 282 is not asserted. When the voltage acrossresistor 281 is greater than the reference voltage, the signal at theoutput of differential amplifier 282 is asserted. Consequently, when thevoltage across resistor 281 is equal to the reference voltage, theoutput signal of differential amplifier 282 transitions from low to high(if the voltage across resistor 281 is increasing) or from high to low(if the voltage across resistor 281 is decreasing.)

The output signal from differential amplifier 282 is provided to DIP DSP210. When the output signal of differential amplifier 282 transitionsfrom low to high (or from high to low,) DIP DSP 210 determines the valueof the test signal produced by signal generator 211. The value of thetest signal at the transition corresponds to the known speaker current,so it can be used to determine the impedance of the speaker. Morespecifically, the impedance of the speaker is calculated by multiplyinga proportionality constant times the ratio of the POM PCM test signalvalue and the voltage across resistor 281 (which is equal to thereference voltage.)

It should be noted that the impedance of the speaker isfrequency-dependent. Consequently, the determination of the speakerimpedance is performed with a test signal that has a constant frequencyand a variable amplitude. It is preferred that the test signal be a sinewave having the selected frequency. The amplitude of the test signal isinitially low and is increased until the voltage drop across resistor281 matches the reference voltage, and the corresponding test signalvalue is determined. The POM PCM test signal value is then used todetermine the impedance of the speaker at the frequency of the testsignal.

The method implemented by the system of FIG. 2 is summarized in the flowdiagram of FIG. 3. As shown in FIG. 3, a POM PCM test signal is firstgenerated (block 310.) As noted above, the test signal is preferably asine wave having a fixed frequency. The test begins with the test signalat an initial amplitude, but the amplitude will be varied as describedbelow. The digital POM PCM test signal is processed by the POM PWMamplifier (block 320) to generate an analog signal suitable for drivinga speaker. This processing includes converting the POM PCM signal to aPOM PWM signal and driving an output stage with the POM PWM signal toproduce the analog output signal. The POM PWM amplifier may also beconfigured to filter the audio signal at various stages within theamplifier.

The analog output signal is then used to drive the speaker (block 330,)and the current through the speaker is monitored to determine whetherthe current has reached/exceeded a threshold level (block 340.) In theembodiment of FIG. 2, this is achieved by comparing the voltage across asense resistor that is placed in series with the speaker to a referencevoltage. The difference between the sense resistor voltage and thereference voltage is amplified to produce a binary signal that is lowwhen the sense resistor voltage is less than the reference voltage andhigh when the sense resistor voltage is greater than the referencevoltage. The transition of this binary signal from low to high indicatesthat the sense resistor voltage is equal to the reference voltage. Ifthe binary signal is low, the amplitude of the test signal is increasedslightly (block 350.) The increased-amplitude signal is processed by thePOM PWM amplifier (block 320) and used to drive the speaker (block 330.)This process continues until the sense resistor voltage is greater thanthe reference voltage.

When the sense resistor voltage is greater than the reference voltage,the speaker current is determined to be equal to (or just greater than)a threshold level (block 340.) This is indicated by the transition ofthe binary signal from low to high. The binary signal is provided to theDIP DSP and, when the signal transitions from low to high, the DIP DSPrecords the value of the POM PCM signal at the test signal generatorthat caused the transition (block 360.) This may be accomplished, forexample, by generating an interrupt when the transition is detected. Thecorresponding value of the POM PCM signal corresponds to the knownthreshold current level through the speaker. The value of the POM PCMsignal and the threshold current level through the speaker are then usedto calculate the impedance of the speaker (block 370.) Based upon thecalculated impedance of the speaker, the response of the amplifier canbe adjusted (e.g., to compensate for high-frequency peaking ordrooping.)

Because the impedance of the speaker varies with frequency, it may bedesirable to determine the impedance of the speaker at more than asingle frequency. If so, then the same procedure described above can berepeated at one or more other frequencies. The resulting impedancevalues form an impedance profile (as a function of frequency) for thespeaker. The impedance profile can be used as the basis for modifyingthe frequency response of the amplifier to optimize the performance ofthe amplifier for use with the speaker.

Referring to FIG. 4, a flow diagram illustrating a method for generatingan impedance profile for a speaker is shown. The method of FIG. 4 beginswith the selection of a frequency at which an initial test will beperformed (block 410.) The impedance at this initial frequency is thendetermined (block 420.) This may, for example, involve using the methoddescribed in connection with FIG. 3 at the initial frequency. After theimpedance is determined for the initial frequency, it is determinedwhether there are additional frequencies for which the speaker impedanceshould be calculated (block 430.) If impedances should be determined foradditional frequencies, then a new frequency is selected (block 440.)The impedance for the new frequency is determined (block 420) and theprocess is repeated for as many additional frequencies as desired. Itshould be noted that the reference voltage need not be changed for thedifferent test signal frequencies.

When there are no additional frequencies for which the impedance of thespeaker needs to be determined (see block 430,) theimpedance-versus-frequency data points are combined to form an impedanceprofile for the speaker (block 450.) The impedance profile is then usedto modify the frequency response of the speaker, if necessary, tooptimize the response of the amplifier for the speaker (block 460.)

It should be noted that the manner in which the frequency response ofthe amplifier is modified may vary from one embodiment to another. Forexample, the amplifier may implement filters (e.g., a band of parametricequalizers) or other mechanisms to change the frequency response. In oneembodiment, the amplifier may initially be optimized for a firstspeaker, and may therefore have a frequency response that complementsthe impedance profile of the first speaker. If the impedance profile ofthe speaker that is actually connected to the amplifier is differentfrom that of the first speaker, the amplifier can change the filteringof the audio signal to compensate for the differences between the firstand actual impedance profiles.

In another embodiment, an amplifier may store a collection (a library)of impedance profiles for known speakers. These impedance profiles maybe generated using any suitable methods, such as those described above.The impedance profiles may alternatively be derived from data sheets orother sources of information for the speakers. In addition to theimpedance profiles, the amplifier stores operating parameters (e.g.,frequency response data) for the speakers. For each impedance profile,there are one or more corresponding operating parameters that arestored. In this embodiment, when an impedance profile is generated for aspeaker that is connected to the amplifier, the amplifier compares thegenerated impedance profile to the impedance profiles that are stored inthe library. If the profile of the actual speaker matches one of thelibrary profiles, the operating parameters corresponding to the matchinglibrary profile are selected and implemented in the amplifier in orderto optimize the performance of the amplifier.

It should be noted that the operating parameters discussed in thepreceding paragraph may include a variety of different things thataffect the performance of the system, such as frequency responsecompensation, signal timing alignment, crossover parameters, and so on.These operating parameters affect the specific manner in which theamplifier performs with respect to particular system characteristics.These may include any number of characteristics that a system designermight wish to “fine tune” in the amplifier, but which cannot beoptimized without knowing the specific characteristics of the speaker(s)that are connected to the amplifier. This feature allows the designer tofine tune the amplifier's performance for a variety of differentspeakers and, when the amplifier determines which speaker is actuallyconnected to the amplifier, the corresponding operating parameters canbe implemented in order to optimize the performance of the system.

In another embodiment, an amplifier includes means to accumulate andprocess the results of multiple tests in order to improve the accuracyof the speaker current measurement. For example, theaccumulation/processing means may consist of an integrator that isconfigured to process the binary over-threshold signal and to provide aresulting signal to a variable gain block. This is illustrated in FIG.5.

Referring to FIG. 5, a functional block diagram illustrating a digitalPOM PWM amplifier in accordance with one alternative embodiment isshown. In this figure, a DIP DSP 510 includes a test signal generator511 which is configured to generate pulse code modulated (POMPCM) testsignals. Rather than being provided directly to POM PWM engine 540, thePOM PCM signal is provided to a variable gain block 530. Variable gainblock 530 adjusts the gain of the POM PCM signal according to a controlsignal received from integrator 520. the gain-adjusted POM PCM signal isthen provided to POM PWM engine 540, which converts the stream of POMPCM audio data into POM PWM audio data. The POM PWM data is provided todriver/level shifter 550, which produces a pair of signals to driveoutput stage/speaker 560.

As in the embodiment of FIG. 2, a sense resistor 581 is placed in serieswith the speaker, and the voltage across resistor 581 is provided to adifferential amplifier 582. Differential amplifier 582 then generatesthe over-threshold signal that indicates whether the voltage acrossresistor 581 is higher or lower than a reference voltage which is alsoprovided to the differential amplifier. The over-threshold signalproduced by differential amplifier 582 is provided to integrator 520which, as noted above, processes the binary over-threshold signal andprovides the resulting control signal to variable gain block 530.

This embodiment forms a closed loop system that regulates the outputsignal level as a function of the output impedance. The lower theimpedance, the lower the output signal level. With a continuous testsignal, the control voltage becomes representative of the outputimpedance. The control loop provides real-time averaging over thousandsof measurements, which greatly increases the accuracy and repeatabilityof the current (or impedance) measurement. This control loop also hasthe advantage of requiring minimal maintenance on the part of the DIPDSP.

In one embodiment, the same closed-loop mechanism described above can beused to enhance impedance detection during a test mode and to providecircuit protection in an operational mode. In the test mode, a very lowreference voltage is used in the comparison with the voltage across thesense resistor. This is sufficient to provide the necessary informationto determine the impedance of the output load. When the system exits thetest mode and enters the operational mode, the reference voltage isincreased to a level that is equal to the resistance of the senseresistor times an upper current threshold. This threshold may, forexample, be a maximum allowable current. In this case, the differentialamplifier (or other comparator) compares the sense resistor voltage tothe reference voltage and generates an output signal that indicateswhether the load current has exceeded the maximum threshold. If so, thenthe amplifier may be configured to take such action as shutting down orlimiting the current in order to avoid damage to the system.

Another alternative embodiment is designed to reduce the impact oferrors that arise from variability in the amplifier. The accuracy ofcurrent/impedance measurements is affected by the tolerances andinaccuracies of various components in the system. For instance, theremay be variations in the output power supply voltage, in the referencevoltage level, and in the resistance of the sense resistor. Thisalternative embodiment provides a mechanism to effectively cancel theseerrors out of the system's measurements.

This embodiment makes use of several ideas to reduce the effects ofvariability in the system. One of the ideas makes use of the fact thatthe current through the sense resistor is trapezoidal. (“Trapezoidal” asused here refers to the fact that the speaker current passes through aninductive element that causes the current to increase or decreaselinearly, as shown in FIG. 6.) The current therefore has a low frequencyaudio component and a high frequency ripple component due to the CL LCfilter in the output. This at first appears to be problematic because,at very low levels of audio, the magnitude of the ripple voltage is muchgreater than the audio contribution. The amplifier, however, employs adebounce mechanism that causes the over-threshold signal to be passed tothe DIP DSP only if the signal is asserted by the comparator for aminimum interval (a selected amount of time or number of cycles.) As aresult, the signal does not “bounce” between asserted and deassertedstates. By carefully adjusting the debounce counters that process theover-threshold signal, audio components of the signal can bediscriminated from the ripple voltage even when the reference voltage isset well below the level of the ripple voltage. It should be noted thatthe same debounce mechanism used for this purpose during testing usedfor other purposes during normal operation of the amplifier.

Another idea of which this embodiment takes advantage is the use ofmultiple debounce timing values. In this embodiment, readings are madewith the debounce timing set to use two different values. Then, ratherthan processing the actual readings, the measurement ratio is used. As aresult, many of the variables which cannot be controlled, includingseveral of the largest error contributors, cancel out in themathematical equations that are applied. The calculations becomeinsensitive to power supply, the absolute value of the reference voltageand the sense resistor value. The equations are instead a function ofoutput filter components and debounce timing, both of which can beaccurately controlled.

Only a few of the possible embodiments of the invention have beendiscussed in this disclosure. Many alternative embodiments are possible,and many will be apparent to persons of skill in the art of theinvention upon reading this disclosure. It should also be noted that thevarious components of the systems described above should be construedbroadly to include comparable components. For instance, while theforegoing description refers to speakers, this should be construed toinclude other types of output loads (e.g., subsequent amplifiers) aswell. Similarly, references to the DIP DSP should be construed toinclude other types of processors and/or control circuitry, referencesto the differential amplifier should be construed to include other typesof comparators, and so on.

Those of skill in the art will understand that information and signalsmay be represented using any of a variety of different technologies andtechniques. For example, data, instructions, commands, information,signals, bits, symbols, and chips that may be referenced throughout theabove description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields orparticles, or any combination thereof. The information and signals maybe communicated between components of the disclosed systems using anysuitable transport media, including wires, metallic traces, vias,optical fibers, and the like.

Those of skill will further appreciate that the various illustrativelogical blocks, modules, circuits, and algorithm steps described inconnection with the embodiments disclosed herein may be implemented aselectronic hardware, computer software, or combinations of both. Toclearly illustrate this interchangeability of hardware and software,various illustrative components, blocks, modules, circuits, and stepshave been described above generally in terms of their functionality.Whether such functionality is implemented as hardware or softwaredepends upon the particular application and design constraints imposedon the overall system. Those of skill in the art may implement thedescribed functionality in varying ways for each particular application,but such implementation decisions should not be interpreted as causing adeparture from the scope of the present invention.

The various illustrative logical blocks, modules, and circuits describedin connection with the embodiments disclosed herein may be implementedor performed with general purpose processors, digital signal processors(DSPs) or other logic devices, application specific integrated circuits(ASICs), field programmable gate arrays (FPGAs), discrete gates ortransistor logic, discrete hardware components, or any combinationthereof designed to perform the functions described herein. A generalpurpose processor may be any conventional processor, controller,microcontroller, state machine or the like. A processor may also beimplemented as a combination of computing devices, e.g., a combinationof a DIP DSP and a microprocessor, a plurality of microprocessors, oneor more microprocessors in conjunction with a DIP DSP core, or any othersuch configuration.

The steps of the methods or algorithms described in connection with theembodiments disclosed herein may be embodied directly in hardware, insoftware or firmware modules executed by a processor, or in acombination thereof. A software product may reside in RAM memory, flashmemory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, aremovable disk, a CD-ROM, or any other form of storage medium known inthe art. An exemplary storage medium is coupled to the processor suchthe processor can read information from, and write information to, thestorage medium. In the alternative, the storage medium may be integralto the processor. The processor and the storage medium may reside in anASIC. The ASIC may reside in a user terminal. In the alternative, theprocessor and the storage medium may reside as discrete components in auser terminal.

The previous description of the disclosed embodiments is provided toenable any person skilled in the art to make or use the presentinvention. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the invention. Thus, the present invention is notintended to be limited to the embodiments shown herein but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

The benefits and advantages which may be provided by the presentinvention have been described above with regard to specific embodiments.These benefits and advantages, and any elements or limitations that maycause them to occur or to become more pronounced are not to be construedas critical, required, or essential features of any or all of theclaims. As used herein, the terms “comprises,” “comprising,” or anyother variations thereof, are intended to be interpreted asnon-exclusively including the elements or limitations which follow thoseterms. Accordingly, a system, method, or other embodiment that comprisesa set of elements is not limited to only those elements, and may includeother elements not expressly listed or inherent to the claimedembodiment.

While the present invention has been described with reference toparticular embodiments, it should be understood that the embodiments areillustrative and that the scope of the invention is not limited to theseembodiments. Many variations, modifications, additions and improvementsto the embodiments described above are possible. It is contemplated thatthese variations, modifications, additions and improvements fall withinthe scope of the invention as detailed within the following claims.

1. A method implemented in a digital amplifier comprising: (a)generating a digital test signal; (b) converting the digital test signalto an analog signal; (c) driving a load with the analog signal; (d)detecting a threshold level of current through the load; (e) identifyinga value of the digital test signal that generated the threshold level ofcurrent through the load; and (f) calculating an impedance of the loadbased on the threshold level of current through the load and thecorresponding value of the digital test signal.
 2. The method of claim1, wherein detecting a threshold level of current through the loadcomprises comparing a measured analog signal corresponding to the levelof current through the load to an analog reference signal correspondingto the threshold level of current and generating a binary signal thatindicates whether the measured analog signal exceeds the analogreference signal.
 3. The method of claim 1, further comprising repeating(a)-(f) with multiple digital test signals having different frequenciesand one or more threshold levels of current through the load, andcalculating an impedance profile of the load based on the thresholdlevels of current through the load and the corresponding values of thedigital test signals.
 4. The method of claim 3, further comprisingcomparing the calculated impedance profile of the load to a library ofimpedance profiles and selecting one of the impedance profiles in thelibrary that matches the calculated impedance profile of the load. 5.The method of claim 4, further comprising implementing a set ofoperating parameters in the digital amplifier that is associated withthe selected one of the impedance profiles in the library.
 6. The methodof claim 1, wherein the digital test signal comprises a pulse codemodulated (PCM) signal and converting the digital test signal to theanalog signal comprises converting the PCM signal to a pulse widthmodulated (PWM) signal and converting the PWM signal to the analogsignal.
 7. The method of claim 6, wherein detecting the threshold levelof current through the load comprises comparing a voltage across a senseresistor that is in series with the load to a reference voltage that isequal to a resistance of the sense resistor times the threshold level ofcurrent.
 8. The method of claim 7, further comprising asserting a binarysignal when the voltage across the sense resistor exceeds the referencevoltage.
 9. The method of claim 7, further comprising asserting aninterrupt when the voltage across the sense resistor exceeds thereference voltage.
 10. A method comprising: in a test mode, generating adigital test signal, converting the digital test signal to an analogtest signal, applying the analog test signal across a load and a senseresistor, comparing a voltage across the sense resistor to a firstreference voltage, wherein the first reference voltage is equal to aresistance of the sense resistor times a first threshold level ofcurrent, generating a binary signal indicating whether the voltageacross the sense resistor exceeds the first reference voltage,identifying a value of the digital test signal that causes the binarysignal to transition between high and low states, and calculating animpedance of the load based on the first threshold level of current andthe identified value of the digital test signal; in an operational mode,converting a digital audio digital test signal to an analog audiosignal, applying the analog signal across a load and a sense resistor,comparing a voltage across the sense resistor to a second referencevoltage, wherein the second reference voltage is equal to a resistanceof the sense resistor times a second threshold level of current which ishigher than the first threshold level of current, generating a binarysignal indicating whether the voltage across the sense resistor exceedsthe second reference voltage, and taking a protective action to limitthe load current when the binary signal indicates that the voltageacross the sense resistor exceeds the second reference voltage.
 11. Themethod of claim 10, wherein the protective action comprises at leasttemporarily shutting down the amplifier.
 12. A digital amplifiercomprising: a digital test signal generator configured to generate adigital test signal; an engine configured to convert the digital testsignal to an analog signal; an output stage configured to receive theanalog signal and to drive a load and a sense resistor in series withthe load with the analog signal; a reference voltage generatorconfigured to generate a reference voltage equal to a resistance of thesense resistor times a threshold level of current; a comparatorconfigured to compare a voltage across the sense resistor to thereference voltage and to generate a binary signal indicating whether thevoltage across the sense resistor exceeds the reference voltage; aprocessor configured to identify a value of the digital test signalcorresponding to a transition in the binary signal and to calculate animpedance of the load based on the threshold level of current and thevalue of the digital test signal corresponding to the transition in thebinary signal.
 13. The digital amplifier of claim 12, wherein thevoltage across the sense resistor and the reference voltage compriseanalog signals.
 14. The digital amplifier of claim 12, wherein thedigital test signal generator is configured to generate digital testsignals of different frequencies for multiple tests; and wherein theprocessor is configured to identify values of each digital test signalcorresponding to transitions in the binary signal and to calculateimpedances of the load for each test signal frequency based on thethreshold level of current and the value of each digital test signalcorresponding to transitions in the binary signal.
 15. The digitalamplifier of claim 14, wherein the processor is configured to comparethe calculated impedances for each test signal frequency to a library ofimpedance profiles and to select one of the impedance profiles in thelibrary that matches the calculated impedances of the load.
 16. Thedigital amplifier of claim 15, wherein the processor is furtherconfigured to implement a set of operating parameters in the digitalamplifier that is associated with the selected one of the impedanceprofiles in the library.
 17. The digital amplifier of claim 12, whereinthe digital test signal generator is configured to generate a pulse codemodulated (PCM) signal and the engine configured to convert the digitaltest signal to an analog signal comprises a pulse width modulated (PWM)engine.
 18. The digital amplifier of claim 12, wherein the processor isconfigured to assert an interrupt when the binary signal transitionsfrom low to high.
 19. The digital amplifier of claim 18 12, furthercomprising an accumulator configured to receive the binary signal and toassert an output signal to the processor only if the binary signal isasserted for a predetermined interval.
 20. The digital amplifier ofclaim 12, wherein: in a test mode, the reference voltage generator isconfigured to generate a first reference voltage equal to a resistanceof the sense resistor times a first threshold level of current below amaximum current level, and the processor is configured to calculate theimpedance of the load based on the threshold level of current and thevalue of the digital test signal corresponding to the transition in thebinary signal; and in an operational mode, the reference voltagegenerator is configured to generate a second reference voltage equal toa resistance of the sense resistor times a second threshold level ofcurrent which is higher than the first threshold level of current; andthe processor is configured to take action to limit the current throughthe load when the binary signal is asserted.
 21. A method implemented ina digital amplifier comprising: (a) generating a digital test signalhaving a corresponding value; (b) converting the digital test signal toan analog test signal that drives a load; (c) sensing a test voltageindicative of a current that flows through the load in response to theanalog test signal driving the load; (d) adjusting the value of thedigital test signal, to thereby adjust an amplitude of the analog testsignal driving the load, until the sensed test voltage reaches areference voltage; and (e) calculating an impedance of the load independence on the value of the digital test signal that causes thesensed test voltage to reach the reference voltage.
 22. The method ofclaim 21, further comprising: (f) modifying a response of the digitalamplifier in dependence of the calculated impedance of the load.
 23. Themethod of claim 22, wherein step (f) includes modifying the response ofthe digital amplifier to compensate for high-frequency peaking and/ordrooping.
 24. The method of claim 21, wherein: the analog test signalthat drives the load has a corresponding frequency; and steps (a), (b),(c), (d) and (e) are performed for each of a plurality of differentfrequencies of the analog test signal to thereby calculate an impedanceprofile of the load.
 25. The method of claim 24, further comprising: (f)modifying a response of the digital amplifier in dependence of thecalculated impedance profile of the load.
 26. The method of claim 21,wherein to reduce effects of variability in the digital amplifier: step(e) comprises calculating the impedance of the load in dependence on thevalue of the digital test signal that causes the sensed test voltage toreach the reference voltage for at least a predetermined interval. 27.The method of claim 21, wherein: the reference voltage is generated independence on a threshold level of current; and the calculating theimpedance of the load at step (e) is also in dependence on the thresholdlevel of current.
 28. The method of claim 27, further comprisinggenerating the reference voltage in dependence on the threshold level ofcurrent.
 29. The method of claim 21, wherein: the load comprises aspeaker; and the analog test signal comprises an analog audio testsignal that drives the speaker.
 30. The method of claim 29, wherein: thedigital test signal generated at step (a) comprises a digital pulse codemodulated (PCM) audio test signal; and at step (b) the digital PCM testsignal is converted to an analog pulse width modulated (PWM) audio testsignal that drives the speaker.
 31. A digital amplifier comprising:circuitry configured to convert a digital test signal to an analog testsignal that drives a load; further circuitry configured to sense a testvoltage indicative of a current that flows through the load in responseto the analog test signal driving the load; and a processor configuredto adjust a value of the digital test signal, to thereby adjust anamplitude of the analog test signal driving the load, until the sensedtest voltage reaches a reference voltage; and calculate an impedance ofthe load in dependence on the value of the digital test signal thatcauses the sensed test voltage to reach the reference voltage.
 32. Thedigital amplifier of claim 31, wherein the processor is also configuredto modify a response of the digital amplifier in dependence of thecalculated impedance of the load.
 33. The digital amplifier of claim 31,further comprising: a digital test signal generator that generates thedigital test signal for each of a plurality of different frequencies, sothat the load is driven by the analog test signal for each of theplurality of different frequencies; wherein the processor is configuredto calculated an impedance profile of the load, in dependence of thevalues of the digital test signal that cause the sensed test voltage toreach the reference voltage for the plurality of different frequencies;and wherein the digital signal generator can be implemented by theprocessor.
 34. The digital amplifier of claim 33, wherein the processoris also configured to modify a response of the digital amplifier independence of the calculated impedance profile of the load.
 35. Thedigital amplifier of claim 31, wherein to reduce effects of variabilityin the digital amplifier, the processor calculates the impedance of theload in dependence on the value of the digital test signal that causesthe sensed test voltage to reach the reference voltage for at least apredetermined interval.